//////////////////////////////////////////////////////////////////////
////                                                              ////
////  CFCOR.v                                                     ////
////                                                              ////
////                                                              ////
////  This file is part of the "Pico E12" project                 ////
////  http://www.picocomputing.com                                ////
////                                                              ////
////                                                              ////
//////////////////////////////////////////////////////////////////////
////                                                              ////
//// Copyright (C) 2005, Picocomputing, Inc.                      ////
//// http://www.picocomputing.com/                                ////
////                                                              ////
//// This source file may be used and distributed without         ////
//// restriction provided that this copyright statement is not    ////
//// removed from the file and that any derivative work contains  ////
//// the original copyright notice and the associated disclaimer. ////
////                                                              ////
//// This source file is free software; you can redistribute it   ////
//// and/or modify it under the terms of the GNU Lesser General   ////
//// Public License as published by the Free Software Foundation; ////
//// either version 2.1 of the License, or (at your option) any   ////
//// later version.                                               ////
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//// This source is distributed in the hope that it will be       ////
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
//// PURPOSE.  See the GNU Lesser General Public License for more ////
//// details.                                                     ////
////                                                              ////
//// You should have received a copy of the GNU Lesser General    ////
//// Public License along with this source; if not, download it   ////
//// from http://www.opencores.org/lgpl.shtml                     ////
////                                                              ////
////////////////////////////////////////////////////////////////////JF

`timescale 10ns / 1ns
`include "PicoDefines.v"

//This module handles the configuration registers which control the I/O base address

module CFCOR(AttribRead, AttribWrite, A, DataIn, DataOut);

input AttribRead;                                      //Configuration Memory Read
input AttribWrite;                                     //Configuration Memory Write
input [10:1]A;                                         //Address Bus (Ignore LSB)
input [7:0]DataIn;                                     //Data Bus In from Host
output [15:0]DataOut;                                  //Data Bus Out to Host

reg [7:0]COA1;                                         //This is the configuration option register it is REQUIRED by the PCMCIA specification
reg [7:0]COA2;                                         //This is the configuration option register it is REQUIRED by the PCMCIA specification

wire COA1Read;                                          //Configuration Option Register Read
wire COA2Read;                                          //Configuration Option Register Read

wire [7:0]DataOutCOA1Read;
wire [7:0]DataOutCOA2Read;

assign COA1Read = (AttribRead) && (A[10:1] == `COA1_ADDRESS);
assign COA2Read = (AttribRead) && (A[10:1] == `COA2_ADDRESS);

//--------Write---------//
always @(posedge AttribWrite) begin                            //Handle Writes to Configuration Registers
	if (A[10:1] == `COA1_ADDRESS) COA1[7:0] <= DataIn[7:0];     //Configuration Register Write
else
	if (A[10:1] == `COA2_ADDRESS) COA2[7:0] <= DataIn[7:0];     //Configuration Register Write
end

//---------Read---------//
assign DataOutCOA1Read[7:0] = (COA1Read)?COA1[7:0] : 8'b0;
assign DataOutCOA2Read[7:0] = (COA2Read)?COA2[7:0] : 8'b0;


assign DataOut[7:0] = (DataOutCOA1Read[7:0] | DataOutCOA2Read[7:0]);
assign DataOut[15:8] = (DataOut[7:0]);

endmodule